As the operating speeds of electronic devices, such as memory devices, continues to increase, the timing of digital signals received by the devices has become ever more critical. For example, in a memory device, such as a dynamic random access memory (“DRAM”) device, command, address and write data signals are transmitted to the memory device by a memory controller, and read data signals are transmitted to the memory controller by the memory device. Conventional memory devices generally operate synchronously with a clock signal, which defines the times that the received signals are considered valid. As the operating speed of memory devices continues to increase, the period during which the command, address and write data signals received by the memory device are considered valid has become ever shorter. As a result, it has become more critical to control the timing at which these signal are received by memory devices.
The timing of digital signals, such as command, address and data signals, are adversely affected by “jitter,” which is high frequency phase noise that cause rapid changes in the timing at which transitions of the digital signal occur. Jitter can be caused by a number of sources, such as noise coupled to digital circuits along with a digital signal, which causes the switching time of the digital circuit to vary in a random manner. Jitter can also be caused by variations in the shape of digital signals coupled to digital circuits.
With reference to FIG. 1, a digital signal having the waveform shown by the dotted line may be applied into a signal line. When the digital signal is applied to the signal line, its signal levels vary between voltages 0 and V*. As shown in FIG. 1, the transmitted waveform has a 50% duty cycle between time t0 and time t2. A “double width” pulse then occurs starting at time t2 followed by a return to the original waveform starting at time t4. If the signal line is highly capacitive, the waveform received by a downstream electronic device may have the waveform shown by the solid line in FIG. 1. As a result of the combination of the high frequency of the signal and the high capacitance of the signal line, the received waveform never reaches the full amplitudes of the transmitted waveform. For example, the transmitted signal starts charging the capacitive signal line toward the voltage V* at time t0, which is shown by the dotted arrow at time t0. However, the amplitude of the received signal never reaches the level V* volts. Instead, it reaches the level V1 at time t1, at which time the transmitted signal starts discharging the signal line toward 0 volts, as again shown by the dotted arrow. Again, the amplitude of the received signal never reaches 0 volts. Instead, it reaches the level V2 at time t2, at which time the transmitted signal again starts charging the signal line. Thus, the capacitive signal line charges toward V* volts from V2 volts, and it starts discharging toward 0 volts from V1 volts.
The symmetrical, unvarying shape of the transmitted signal between times t0-t2, causes the received signal to cross the midpoint voltage M with the same delay after each corresponding edge of the transmitted signal. This can be seen by the uniform spacing between the dotted arrows and the immediately following solid arrows. As a result, a digital circuit that switches state at the midpoint voltage M will change state with a uniform delay after each transition of the signal applied to the signal line.
During the double width pulse starting at time t2, the signal line is charged toward the voltage V* for a longer period of time. The received signal therefore reaches the amplitude V3 volts at time t4 at which time the signal line begins being discharged toward 0 volts. The received signal still crosses the midpoint voltage M with the same delay after the corresponding edge of the transmitted signal as shown by the solid arrow following the dotted arrow at time t2. However, because the discharge of the signal line starts from V3 volts rather than the lower amplitude of V1 volts, it now crosses the midpoint voltage M with a much longer delay after the corresponding edge of the transmitted signal. The skew of the received signal can be seen by the increased spacing of the solid arrow immediately following the dotted arrow at time t4. This skew in the midpoint amplitude M crossing delay as function of the bit pattern of the transmitted signal can results in signal jitter at a circuit receiving the signal. As explained above, jitter can adversely affect the receiving circuit's ability to capture the correct pattern of the transmitted digital signal because the receiving circuit may register the incorrect bit from the received signal.
This jitter problem is particularly acute in coupling address signal to memory devices. Address signal are typically transmitted to a plurality of memory devices through a signal distribution tree. The relatively large size of the tree when a large number of memory devices are present makes the address lines highly capacitive. In fact, the jitter caused by the high capacitance of address signal trees can defeat the major reason for using a tree, i.e., to ensure that address signal transitions arrive at all of the memory devices at the same time. The memory devices in a system attempt to capture the address signals using a clock signal, which may also be coupled through a clock tree. Ideally, a transition of the clock signal used to capture the address signals occurs at the center of the address signal. However, jitter can cause timing skews that cause the clock signal transition to occur before or after a “window” or “eye” during which the address signals are valid. For example, as shown in FIG. 2, if a clock signal CLK does not cause each of several address signals A<0:9> to latch at the proper time, errors in the operation of the memory device may result. Thus, the timing skew of the clock signal CLK relative to the timing skews of the address signals A<0:9> must be limited to allow the CLK signal to latch each of the several address signals A<0:9>. As the data transfer rate increases, the duration of each eye E for which each address signal A<0>-A<9> is valid decreases by a corresponding amount, as will be understood by one skilled in the art. With further reference to FIG. 2, the solid lines indicate the ideal address signals A<0>, A<1>, and A<9> signals, and the dashed lines indicate the worst case potential time skew for each of these signals. The ideal address signals A<0>, A<1>, and A<9> are centered at the rising edge of the CLK signals. The eyes E during which the address signals A<0>, A<1>, and A<9> are valid are defined by time intervals t0-t3, t1-t4, and t5-t7, respectively. In fact, the eyes E of the applied address signals A<0>-A<9> may even vary to such an extent that not all of the address signals are simultaneously valid at any time. In other words, there is no time during which the eyes E of all of the address signals overlap. Under these circumstances, the ideal address signals A<0>, A<1>, and A<9> signals, all of the address signals A<0>-A<9> cannot possibly be captured by the CLK signal. For example, in FIG. 2, the eye E of the A<0> signal from times t0-t3 does not overlap the eye of the A<9> signal from times t5-t7. It is therefore important to limit the jitter or timing skew of the CLK and address signals A<0>-A<9>.
Attempts have been made to solve the jitter problem exemplified by FIGS. 1 and 2 using various equalization techniques. Two different equalization approaches have been tried. The first approach attempts to modify the characteristics of the signal line by either making it less capacitive or by making a transmitted signal less affected by the capacitance, such as by inserting repeaters or inverters in the line. Unfortunately, this approach can unduly increase the cost of digital devices. The second approach attempts to modify the shape of the transmitted signal so that the capacitance of the signal line causes it to be received with close to its original shape. In one example, every transition of the digital signal is provided with a large overshoot, which is capacitively filtered out by the signal line. The size and complexity of circuitry using this approach can again unduly increase the cost of digital devices, particularly since the nature of the modification must depend on the characteristics of the bit pattern.
There is therefore a need for a relatively inexpensive system and method for allowing digital signals having an irregular bit pattern to be coupled through highly capacitive signal lines without causing jitter in the received signal.